1. Field of the Invention
The present invention relates to a process for producing a semiconductor substrate. More specifically, the present invention relates to a process for producing a monocrystalline semiconductor on a dielectric-isolated or insulative material, or a monocrystalline compound semiconductor on a semiconductor substrate. Further the present invention relates to a process for producing an electronic device or an integrated circuit formed on a single crystalline semiconductor layer.
2. Related Background Art
The technique of formation of monocrystalline Si (silicon) semiconductor on an insulative material is well known as silicon-on-insulator (SOI) technique. A device prepared by the SOI technique has various advantages which are not achievable by a bulk Si substrate in usual Si integrated circuits, as noted below:
1. Ease of dielectric isolation, and possibility of high degree of integration' PA1 2. High resistance against radioactive ray; PA1 3. Low floating capacity, and the possibility of high speed operation; PA1 4. The welling process is unnecessary; PA1 5. Preventability of latch-up; and PA1 6. Possibility of producing a complete depletion type field-effect transistor to name a few. PA1 1. A first process which includes surface oxidation of a monocrystalline Si substrate, local exposure of the Si substrate by opening a window, and epitaxial growth of Si laterally from the exposed portion as the seed to form an Si layer on SiO.sub.2. (Si layer deposition on SiO.sub.2). PA1 2. A second process including SiO.sub.2 formation beneath a monocrystalline SiO.sub.2 substrate, utilizing the SiO.sub.2 substrate as the active layer. (No Si layer deposition). PA1 1. An oxidation film is formed on a monocrystalline Si substrate which has V-shaped grooves on the surface formed by anisotropical etching; a polycrystalline Si layer is deposited in a thickness approximate to that of the Si substrate on the oxidation film; and the back face of the Si substrate is ground to form a monocrystalline Si region isolated dielectrically by surrounding with the V-shaped grooves. This method involves problems in controllability and productivity in deposition of polycrystalline Si in a thickness of as large as several hundred microns, and in removal of the monocrystalline Si substrate by grinding at the back face to leave an isolated active Si layer only. PA1 2. An SiO.sub.2 layer is formed by ion implantation into a monocrystalline Si substrate (SIMOX: Separation by ion implanted oxygen). This is the most highly advanced method in view of the matching with the Si process. This method, however, requires implantation of oxygen ions in an amount of as much as 10.sup.18 ions/cm.sup.2, which takes a long time, resulting in low productivity and high wafer cost. Further, the product has many remaining crystal defects, and does not have satisfactory properties for the industrial production of a minority carrier device. PA1 3. An SOI structure is formed by oxidation of porous Si for dielectric isolation. In this method, an N-type Si layer is formed in an island-like pattern on a P-type monocrystalline Si substrate surface by proton ion implantation (Imai, et al.: J. Crystal Growth, Vol. 63, p. 547 (1983)) or by epitaxial growth and patterning, and subsequently only the P-type Si substrate is made porous by anodic oxidation in an HF solution to surround the island-patterned N-type Si, and the N-type Si island is dielectrically isolated by accelerated oxidation. In this method, the isolated Si regions are fixed prior to the device process, which may limit the freedom of device design disadvantageously. PA1 4. Different from the above conventional SOI formation, a method has recently come to be noticed in which a monocrystalline Si substrate is bonded to another thermally oxidized monocrystalline Si substrate by heat treatment or use of an adhesive to form an SOI structure. This method requires uniform thinness of the active layer for the device: namely, formation of a film of a micron thick or thinner from a monocrystalline substrate of several hundred microns thick. This thin film may be formed by either of the two methods below.
The process of forming the SOI structure has been actively studied for several decades. The results of the studies are summarized, for example, in the paper: Special Issue; "Single-crystal silicon on non-single-crystal insulators"; edited by G. W. Cullen, Journal of Crystal Growth; Vol.63, No.3, pp.429-590 (1983).
SOS (silicon on sapphire) is known and is produced by heteroepitaxial growth of silicon on monocrystalline sapphire by CVD (chemical vapor deposition). The SOS technique, which is successful as one of SOI techniques, is limited in its application, because of many crystal defects caused by mismatch of the lattice at the interface between the Si layer and the underlying sapphire, contamination of the Si layer with aluminum from the sapphire substrate, expense of the substrate, and the difficulty of large-area substrate formation.
Recently, studies are being made to produce the SOI structure without using a sapphire substrate. The studies are classified roughly into the two processes below:
The device formed on a compound semiconductor exhibits performances, such as high speed, and luminescence, which are not achievable by Si. Such types of devices are formed by epitaxial growth on a compound semiconductor substrate such as GaAs. The compound semiconductor substrate, however, has disadvantages of high cost, low mechanical strength, and difficulty in the formation of a large-area wafer. Accordingly, heteroepitaxial growth of a compound semiconductor on an Si wafer is being studied to attain low cost, high mechanical strength, and ease of production of a large-area wafer.
The above-known process 1 (Si layer deposition on SiO.sub.2) includes methods of direct lateral epitaxial growth of monocrystalline Si layer by CVD; deposition of amorphous Si and subsequent heat treatment to cause solid-phase lateral epitaxial growth; melting recrystallization to grow monocrystalline layer on an SiO.sub.2 by irradiation of amorphous or polycrystalline Si layer with a focused energy beam such as an electron beam and laser beam; and a zone melting recrystallization in which a bar-shaped heater is moved to scan with a belt-like melt zone. These methods respectively have advantages and disadvantages, involving problems in process controllability, productivity, product uniformity, and product quality, and are not industrialized yet. For example, the CVD method requires sacrificial oxidation, giving low crystallinity in the solid-phase growth. The beam annealing method involves problems in processing time of focused beam scanning and in controllability of beam superposition and focusing. Of the above methods, the zone melting recrystallization is the most advanced method, and is employed in relatively large scale integrated circuits. This method, however, still causes crystal defects in subgrain boundaries, and is not successful in the production of a minority carrier device.
The above known process 2 in which the Si substrate is not utilized as the seed for epitaxial growth includes the four methods below:
1. Thin film formation by grinding; and PA2 2. Thin film formation by selective etching.
The grinding method does not readily give a uniform thin film. In particular, formation of a film of submicron thickness results in thickness variation of tens of percent. This irregularity is a serious problem. With a larger diameter of the wafer, the uniformity of the thickness is much more difficult to attain.
The etching method is regarded to be effective for uniform thin film formation. This method, however, involves the problems of insufficient selectivity of about 10.sup.2 at the highest, inferior surface properties after etching, and low crystallinity of the SOI layer because of the employed ion implantation, epitaxial or heteroepitaxial growth on a high-concentration B-doped Si layer. (C. Harendt, et al.: J. Elect. Mater., Vol. 20, p. 267 (1991); H. Baumgart, et al.: Extended Abstract of ECS 1st International Symposium of Wafer Bonding, pp. 733 (1991); and C. E. Hunt: Extended Abstract of ECS 1st International Symposium of Wafer Bonding, pp. 696 (1991))
The semiconductor substrate which is prepared by lamination requires two wafers essentially, and a major part of one of the wafers is discarded by grinding or etching, thereby wasting the resource. Therefore, the SOI prepared by lamination involves many problems in controllability, uniformity, production cost, and so forth in conventional processes.
A thin Si layer deposited on a light-transmissive substrate typified by a glass plate becomes amorphous or polycrystalline owing to disorder of crystallinity of the substrate, not giving high performance of the device. Simple deposition of Si does not give desired quality of single crystal layer owing to the amorphous crystal structure of the substrate.
The light-transmissive substrate is essential for construction of a light-receiving element such as a contact sensor, and projection type of liquid crystal image-displaying apparatus. Additionally, a driving element of high performance is necessary for higher density, higher resolution, and higher precision of the sensor and of the image elements of the display. Consequently, the element provided on a light transmissive substrate is also required to have a monocrystalline layer of high crystallinity.
Amorphous Si or polycrystalline Si will not give a driving element having the required sufficient performance because of the many defects in the crystal structure.
As mentioned above, a compound semiconductor device requires essentially a compound semiconductor substrate. The compound semiconductor substrate, however, is expensive, and is not readily formed in a larger size.
Epitaxial growth of a compound semiconductor such as GaAs on an Si substrate gives a grown film of poor crystallinity owing to the difference in the lattice constants and the thermal expansion coefficients, thereby the resulting grown film being unsuitable for use for a device.
Epitaxial growth of a compound semiconductor on porous Si is intended for mitigation of mismatch of the lattices. However, the substrate does not have sufficient stability and reliability owing to the low thermal stability and long-term deterioration of the porous Si.
In view of the above-mentioned problems, Takao Yonehara, one of the inventors of the present invention, disclosed formerly a novel process for preparing a semiconductor member in European Patent Publication No. 0469630A2. This process comprises the steps of forming a member having a nonporous monocrystalline semiconductor region on a porous monocrystalline semiconductor region; bonding the surface of a member of which the surface is constituted of an insulating substance onto the surface of the nonporous monocrystalline semiconductor region; and then removing the porous monocrystalline semiconductor region by etching. This process is satisfactory for solving the above-mentioned problems. Further improvement of the disclosed process for higher productivity and lower production cost will contribute greatly to the industries concerned.